Intel announces three new chip packaging technologies to build computing systems of the future
Intel announces three new chip packaging technologies to build computing systems of the future.
The chipmaker has combined its 3D chip stacking technology Foveros with its existing Embedded Multi-die Interconnect Bridge (EMIB) design that supplies 2D connections across the elements on a chip package.
The new amalgamated technology is called Co-EMIB that allows for “high-density interconnects” of two or more Foveros elements to enable energy efficient, high bandwidth communication on a single chip package.
Intel has also developed Omni-Directional Interconnect (ODI) that allows stacked chiplets to communicate efficiently with improved through-silicon vias (TSVs), which feature lower resistance, higher bandwidth and lower latency. ODI also reduces the number of TSVs required and this implementation optimizes die usage for more transistors.
Last of all, Intel builds upon its Advanced Interface Bus (AIB) to deliver a new “die-to-die interface” called MDIO. The company claims the improved physical layer connect will provide “better power efficiency and more than double the pin speed and bandwidth density offered by AIB.” These new advances by Intel should provide more flexibility in building increasingly sophisticated chiplets.
At the same time, they ensure the interoperability across different components from multiple vendors. An example of this is the 8th generation Intel Core i7 and i5 mobile processors, i.e., Kaby Lake G processors.
Source: Intel (1), (2)